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Freescale Semiconductor /MK61F15WS /DDR /CR07

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Interpret as CR07

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKPW0RESERVED0TCKESR0RESERVED 0 (0)AP 0RESERVED0 (0)CCAPEN 0RESERVED

AP=0, CCAPEN=0

Description

DDR Control Register 7

Fields

CLKPW

Clock Pulse Width
RESERVED

Reserved
TCKESR

Time Clock low Self Refresh
RESERVED

Reserved
AP

Auto Precharge

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved
CCAPEN

Concurrent Auto-Precharge Enable

0 (0): Disabled

1 (1): Enabled
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data